Current techniques for connecting chips to one another include using a PC board and connecting the chips via data trace lines. For example, two VLSI chips may be connected via trace lines extending along the PC board between the two chips. One problem with such a configuration includes large capacitance along the trace lines, which lowers bandwidth and increases size of the devices. Heat is also generated with larger capacitance. In addition, I/O capacitance of devices of the chips themselves is relatively high, which further lowers bandwidth and increases heat. Electrical reliability at higher rates is also reduced because digital square waves become rounded. As understood the in art, solder is typically used to connect the chips to the PC board trace lines. Solder inherently increases capacitance and has the ability to have reliability issues due to “cold” solder joints and other well known problem.
System on a chip (SOC) may use flip-chip connection technology between a PC board and VLSI chips. There are various forms of flip-chip technologies that may be utilized. While flip-chip technology offers some level of benefits for improved performance and ease of manufacturing, the trace lines that extend along a PC board result in the same or similar high capacitance, limited bandwidth, and thermal problems as traditional wire bond.
A single chip SOC with major pre-designed and proven SOC building blocks placed and wired in a single chip are also available. While each of the components, including a micro-processor, digital signal processor (DSP), memory, and input/output (I/O) chips, are placed on a single SOC chip, each of the components are still physically spaced apart from one another. As a result, the trace line interconnects are long enough to provide enough capacitance that materially affect bandwidth and cause heat generation. Still yet, because of the spacing between the chips, valuable physical real estate is lost that could otherwise be used for certain functionality and performance for the system. And, because the size of the chip is larger, system level designs are negatively affected, as understood in the art. In addition, because of the larger chip size, manufacturing yields are reduced, which can be very costly due to the cost of such a system on a chip.